A known phase lock loop (PLL) configuration comprises a voltage controlled oscillator (VCO), a phase detector and a loop filter comprising a charge pump and a filter network. The phase detector is responsive to an output signal of the VCO and to a reference signal to generate a control signal which is indicative of a phase difference of the output signal and the reference signal. The charge pump is responsive to the control signal to apply a charge indicative of the phase difference to the filter network, thereby developing a control voltage across the filter network. The control voltage is applied to the VCO to control the frequency of the VCO output signal.
An example of this phase lock loop configuration is disclosed in Jeong et al, IEEE Journal of Solid State circuits, Vol. SC-22, No. 2, April 1987, pp. 255-261.
Unfortunately, the performance of such phase lock loops can vary significantly over a range of operating frequencies or in response to different operating conditions. Moreover, when such phase lock loops are implemented in integrated circuit form, their performance may vary significantly due to parameter changes resulting from slight variations in the manufacturing processes used to fabricate the integrated circuits.